Polycrystalline silicon diode string for ESD protection of different power supply connections

ABSTRACT

An ESD protection circuit protects integrated circuits having multiple power supply voltage sources from damage when an ESD event causes excessive differential voltages between the multiple separate power supply voltage sources. The ESD protection circuit has a string of serially connected lateral polycrystalline silicon diodes characterized by consistent turn-on threshold voltage level such that as the number of stage of the ESD protection circuit increase, the turn-on voltage threshold of the ESD protection circuit increase linearly.

BACKGROUND OF THE INVENTION

[0001] Field of the Invention

[0002] This invention relates to circuits coupled to an integratedcircuit that provides protection from electrostatic discharge (ESD)events. More particularly, this invention relates to circuits that willprevent a differential voltage level between two different power supplyvoltage terminals from exceeding a specified voltage level and thusprevent damage to the integrated circuit.

DESCRIPTION OF RELATED ART

[0003] Integrated circuits often have either multiple terminalsconnected to a single power supply voltage source or multiple isolatedpower supply voltage sources. The power supply voltage sources areconnected through separate distribution networks to the internalintegrated circuits. The structure of the internal integrated circuitsmay have a core logic section and a peripheral logic section. In orderto isolate noise, such as caused by simultaneous switching of drivercircuits in the peripheral logic section or impedance mismatch ontransmission line connected to an input/output (I/O) pad the peripherallogic section would have a separate power supply distribution networkfrom that of the core logic section. Similarly, the internal circuitsmay include analog circuits requiring multiple power supply voltagesources and need to be isolated from the core logic and peripheral logicsection to prevent conduction of noise to the analog circuits.

[0004] While the core logic section and the peripheral logic sectionoften have a common power supply voltage source, it is not uncommon forthe core logic section to have a power supply voltage source of adifferent voltage level than the peripheral logic section. For instance,the peripheral logic section may have a power supply voltage source of5.0V and the core logic section may have a power supply voltage sourceof 3.3V. It is further common that the analog section require evendifferent voltage levels than the core logic section or the peripherallogic section. Further, the internal integrated circuits may haveimplementations with multiple core logic sections, multiple peripherallogic sections, and multiple analog core sections. Each section willhave a separate voltage distribution network for the power source andreturn paths.

[0005] An ESD event is commonly a pulse of a very high voltage typicallyof several kilovolts with a moderate current of a few amperes for ashort period, typically about 100 nanoseconds. The common source of anESD event is bringing the integrated circuit in contact with a humanbody or a machine such as an integrated circuit tester and handler.

[0006] If an I/O pad is contacted and subjected to an ESD event, thepower supply distribution network of the peripheral logic sectionconnected to the I/O pad begins to change relative to the voltage levelof the power supply voltage source connected to the core logic section.This change can cause damage in subcircuits that form an interfacebetween the core logic section and the peripheral logic section. FIG. 1illustrates a structure of the prior art of a voltage clamping circuitemployed to prevent damage between the distribution networks of twoseparate power supply voltage sources. The structure of FIG. 1illustrates a two-staged voltage clamping circuit, which may be expandedby the addition of more stages.

[0007] A substrate has the distribution networks 55 and 60 to connectthe separate power supplies V_(sup1) and V_(sup2) to the internalcircuitry 65. To provide the protection from any ESD events, the voltageclamping circuit is connected between the distribution networks 55 and60 to connect the separate power supplies V_(sup1) and V_(sup2). Thevoltage clamping circuit has an N-type impurity diffused to a lightlydoped level into the P-type substrate 5 to form the N-wells 10 and 15.The N-type impurity is diffused to a high concentration level into theN-wells 10 and 15 to form the heavily doped N-regions 20, 25, 35, and45. A P-type material is diffused to a high concentration into theN-wells 10 and 15 to form the heavily doped P-regions 30 and 40.Simultaneously the P-type material is diffused into the substrate 5 toform the P-region 50. Contact metallurgy is alloyed to the P-type region50 to form a contact that is connected to the ground referencedistribution system 75.

[0008] Contact metallurgy is alloyed to the P-type regions 30 and 40 toform contacts that are respectively connected to the distributionnetworks 55 and 60 for the power supply voltage sources V_(sup1) andV_(sup2) Contact metallurgy is alloyed to the N-type regions 20 and 25and to the P-type region 40 to form a contact that seriallyinterconnects the two stages of the voltage clamping circuit. Contactmetallurgy is alloyed to the N-type regions 35 and 45 to form contactsthat are connected to the distribution network 60 that is connected tothe power supply voltage source V_(sup2).

[0009] The diode D₁ 70 a is formed at the junction of the P-region 30and N-well 10 in conjunction with the N-region 20. Similarly, the diodesD₂ 70 b, D₃ 70 c, and D₄ 70 d are formed at the junction of theP-regions 30 and 40 and N-wells 10 and 15 in conjunction respectivelywith the N-regions 25, 35, and 45. Further the emitter of the verticalPNP transistor 75 a is formed by the P-region 30, the base being theN-well 10, and the collector being the P-type substrate 5. Likewise, theemitter of the vertical PNP transistor 75 b is formed by the P-region40, the base being the N-well 15, and the collector being the P-typesubstrate 5.

[0010] Referring now to FIG. 2 for a discussion of the operation of thevoltage clamping circuit of the prior art. In this example, the voltageclamping circuit has multiple PNP transistors 75 a, 75 b, . . . , 75 m,. . . , 75 n serially connected emitter to base. The emitter of firstPNP transistor 75 a is connected to the distribution network 55 of thepower supply voltage source V_(sup1). The base of the last PNPtransistor 75 n is connected to the distribution network 60 of the powersupply voltage source V_(sup1). The collectors of the PNP transistors 75a, 75 b, . . . , 75 m, . . . , 75 n are connected to the groundreference distribution system 75. If the voltage level present on thedistribution network of the power supply voltage supply V_(sup1)increases to a threshold level greater than the voltage level of thepower supply voltage source V_(sup2), the base-emitter diodes of the PNPtransistors 75 a, 75 b, . . . , 75 m, 75 n begin to conduct to clamp anyvoltage difference between the power supply voltage source V_(sup1), andthe power supply voltage source V_(sup2) to maintain the threshold leveldifference between the power supply voltage sources V_(sup1), andV_(sup2).

[0011] The threshold level is determined by the number of seriallyconnected PNP transistors 75 a, 75 b, . . . , 75 m, . . . , 75 n and iscalculated from the formula:

V _(t) =mV _(d) −V _(o) m*m(m−1)*ln(β+1)/2

[0012] where:

[0013] V_(t) is threshold level of the voltage clamping circuit.

[0014] m is the number of PNP transistors 75 a, 75 b, . . . , 75 m, 75n.

[0015] V_(d) voltage developed across each individual base emitterjunction of the PNP transistors 75 a, 75 b, . . . , 75 m . . . , 75 n.

[0016] V_(o) is determined by the formula $V_{O} = \frac{KT}{q}$

[0017]  where:

[0018] K is Boltzman's constant.

[0019] T is the temperature.

[0020] q is electrical charge of an electron.

[0021] It is known that the main cause in a decrease in the breakdown orconduction voltage of during an ESD event is the leakage current from ofthe base-emitter junction of the PNP transistors 75 a, 75 b, . . . , 75m, . . . , 75 n. Thus, as the number of PNP transistors 75 a, 75 b, . .. , 75 m, . . . , 75 n increases, the threshold level does not increaseconcomitantly.

[0022] Other ESD device structures as illustrated in U.S. Pat. No.5,674,761 (Chang, et al.), U.S. Pat. No. 5,856,214 (Yu), and U.S. Pat.No. 6,096,584 (Ellis-Monaghan, et al.) provide ESD devices structuresthat prevent damage to internal circuitry by preventing excess voltageas applied to input/output pads from damaging internal circuitry.

[0023] Polycrystalline silicon diodes are well known in the art asillustrated by U.S. Pat. No. 4,616,404 (Wang, et al.). Wang, et al.describes a method of making improved lateral polycrystalline silicondiode by treating plasma-etched sidewalls to remove defects. The lateralpolycrystalline diode is characterized by low reverse current leakage, abreakdown voltage of at least five volts, and low series resistancepermitting high current flow before being limited by saturation. Thepolycrystalline silicon diode has a polycrystalline silicon block formedon a substrate. The polycrystalline silicon block has a first zonesufficiently doped to provide a first semiconductor type and a secondzone sufficiently doped to provide a second semiconductor type. Thejunction where the two zones are adjoined form a diode.

[0024] Another polycrystalline diode is described in U.S. Pat. No.6,229,157 (Sandhu). The polycrystalline silicon diode of Sandhu has arelatively improved on-off ratio. The diode is formed in a container inan insulative structure layered on a substrate of an integrated circuit.The container is then partially filled with a polycrystalline siliconmaterial, by methods such as conformal deposition, leaving a generallyvertical seam in the middle of the polycrystalline silicon material. Aninsulative material is deposited in the seam. The polycrystallinesilicon material is appropriately doped and electrical contacts andconductors are added as required. The diode can be coupled to achalcogenide resistive element to create a chalcogenide memory cell.

[0025] A polycrystalline diode structure that has a high voltagetolerance, which is to be used for mixed-voltage, and mixed signal andanalog/digital applications is described in U.S. Pat. No. 6,232,163 andU.S. Pat. No. 6,015,993 (both to Voldman, et al.). The diode includes apolycrystalline silicon gate structure on at least one dielectric filmlayer on a semiconductor (silicon) layer or body. A well or an implantedarea is formed in a bulk semiconductor substrate or in a surface siliconlayer on an SOI wafer. A block mask is formed over the gate structurewhen defining the depleted-polycrystalline silicon gate silicon diode toform low series resistance diode implants, preventing over-doping thefilm.

[0026] An application of polycrystalline silicon diodes is shown in“On-Chip ESD Protection Design by Using Polysilicon Diodes in CMOSProcess,” Ker et al., IEEE Journal Of Solid-State Circuits, IEEE, NewYork, N.Y., VOL. 36, NO. 4, April 2001, pp. 676-686 and “On-Chip ESDProtection Design for GHz RF Integrated Circuits by UsingPolycrystalline silicon Diodes in subquarter-micron CMOS Process,” Changand Ker, Proceedings 2000 Electrical Overstress and ElectrostaticDischarge Symposium, IEEE, New York, N.Y., 2000, pp. 3A 4.1-3A 4.10.These papers describe applications using polycrystalline silicon diodesas the ESD clamp devices in CMOS process. Different process factors areexperimentally evaluated to find the suitable doping concentration foroptimizing the polycrystalline silicon diodes for both on-chip ESDprotection design and the application requirements of the smart-cardIC's.

[0027] Another application for polycrystalline silicon diodes for ESDapplications is described in “Design of the Turn-On Efficient Power-RailESD Clamp Circuit with Stacked Polysilicon Diodes,” Ker and Chen,Proceeding of the 2001 International Symposium on Circuits and Systems,IEEE, New York, 2001, pp. IV-758-IV-761. Ker and Chen detail a novelpower-rail ESD clamp circuit design by using stacked polycrystallinesilicon diodes to trigger ESD protection device is proposed to achieveexcellent on-chip ESD protection. The power-rail ESD clamp circuitemploying the polycrystalline silicon diodes as described in Ker andChen achieves a human body model ESD level has been successfullyimproved from the original ˜200V to become 3 Kv.

SUMMARY OF THE INVENTION

[0028] An object of this invention is to provide an ESD protectioncircuit that will protect integrated circuits having multiple powersupply voltage sources from damage when an ESD event causes excessivedifferential voltages between the multiple separate power supply voltagesources.

[0029] Another object of this invention is to provide an ESD protectioncircuit having a lateral diode constructed of polycrystalline siliconcharacterized by consistent turn-on threshold voltage level such that asthe number of stage of the ESD protection circuit increase, the turn-onvoltage threshold of the ESD protection circuit increase linearly.

[0030] To accomplish at least one of these objects as well as otherobjects, an electrostatic discharge circuit that includes a plurality ofserially connected polycrystalline silicon diodes formed on a surface ofa substrate is connected between a first power supply voltage source anda second power supply voltage source to protect internal integratedcircuits from damage due to an electrostatic discharge. Each diode ofthe plurality of serially connected polycrystalline diodes has a firstelectrode and a second electrode. The plurality of serially connectedpolycrystalline diodes has a first diode, which has its first electrodeconnected to the first power supply voltage source, and a last diode,which has its second electrode connected to the second power supplyvoltage source.

[0031] The first electrode of each diode of the plurality of seriallyconnected polycrystalline silicon diodes is a first region ofpolycrystalline silicon being heavily doped with an impurity of a firsttype. Further, the second electrode of each diode of the plurality ofserially connected polycrystalline diodes is a second region ofpolycrystalline silicon being heavily doped with an impurity of a secondtype. The second region being adjoined to the first region to form anelectrical junction. Each diode is formed on a shallow trench isolationformed within the substrate. During formation of each diode a resistorprotection oxide formed as an overlay to protect a portion of the firstand second regions at the junction.

[0032] Generally, the first electrode of each polycrystalline silicondiode is defined as cathode and the second electrode of eachpolycrystalline silicon diode is defined as an anode. To maintain thisdefinition, the impurity of the first type is an N-type impurity havinga density of from approximately 10¹⁵ atoms/cm⁻³ to approximately 10²¹atoms/cm⁻³. The impurity of the second type is a P-type impurity havinga density of from approximately 10¹⁵ atoms/cm⁻³ to approximately 10²¹atoms/cm⁻³.

[0033] The width of each of the diodes and the thickness of thepolycrystalline silicon diodes and the doping levels of the first andsecond electrodes of each diode determines the resistivity of the diodeand thus the current capacity of the diodes. The preferred thickness ofthe polycrystalline silicon diodes is preferably from approximately 1000Å to approximately 3000 Å. The width of polycrystalline silicon diodesis preferably from approximately 0.5 μm to approximately 100 μm.

[0034] The number of the plurality of serially connected polycrystallinesilicon diodes of the electrostatic discharge circuit is determined bythe formula: $n \geq \frac{V_{noise} + {{{Vx1} - {Vx2}}}}{V_{T}}$

[0035] where:

[0036] n is the number serially connected of polycrystalline silicondiodes,

[0037] V_(noise) is the maximum voltage level difference allowed to bepresent on the internal integrated circuits between the first powersupply voltage source and the second power supply voltage source,

[0038] Vx1 is the magnitude of the first power supply voltage source,

[0039] Vx2 is the magnitude of the second power supply voltage source,and

[0040] V_(T) is the threshold voltage of each polycrystalline silicondiodes.

BRIEF DESCRIPTION OF THE DRAWINGS

[0041]FIG. 1 is a cross sectional view of the structure of an ESDprotection circuit of the prior art.

[0042]FIG. 2 is an schematic of an equivalent circuit of the ESDprotection circuit of the prior art as described in FIG. 1

[0043]FIG. 3 is plot of the ESD protection circuit of the prior artillustrating the current through a number of stages of the ESDprotection circuit versus the voltage across the ESD protection circuitof the prior art.

[0044]FIG. 4a is an schematic of an equivalent circuit of the ESDprotection circuit of this invention as described in FIG. 4a

[0045]FIG. 4b is a cross sectional view of the structure of an ESDprotection circuit of this invention.

[0046]FIGS. 5a-5 o are cross sectional views of a semiconductorsubstrate illustrating the method of the formation of thepolycrystalline silicon diodes as they form the ESD protection circuitof this invention.

[0047]FIGS. 6a-6 b are top views of a semiconductor substrateillustrating the method of the formation of the polycrystalline silicondiodes as they form the ESD protection circuit of this invention.

[0048]FIG. 7 is plot of the ESD protection circuit of this inventionillustrating the current through a number of stages of the ESDprotection circuit versus the voltage across the ESD protection circuitof this invention.

DETAILED DESCRIPTION OF THE INVENTION

[0049] The ESD protection circuit of this invention is constructed toprovide a path having a low leakage current during normal operation anda path having a consistent turn-on threshold voltage level such that asthe number of stages or diodes of the ESD protection circuit increases,the turn-on threshold voltage level increases linearly. The ESDprotection circuit consists of a string of serially connectedpolycrystalline silicon diodes D₁, D₂, D₂, . . . , D_(n-1), D_(n)coupled between the interconnection networks of a two separate powersupply voltage sources V_(sup1) and V_(sup2) as shown in FIG. 4a.

[0050]FIG. 4b illustrates the structure of the serially connectedpolycrystalline silicon diodes of this invention. Regions of shallowtrench isolation 110 a 110 b are formed in the P-type substrate 105.Even though multiple regions of shallow trench isolation 110 a 10 b areshown, the serially connected polycrystalline silicon diodes maybeformed on a single region of shallow trench isolation 110 a 110 b.

[0051] Segments of polycrystalline silicon 115 a and 115 b are formed onthe surface of each region of STI 100 a and 110 b. The segments ofpolycrystalline silicon 115 a and 115 b have regions 120 a and 120 bheavily doped with a P-type material to form an anode of thepolycrystalline silicon diodes D₁, D₂, D₃, . . . , D_(n-1), D_(n). Theregions 125 a and 125 b of the segments of the polycrystalline silicon115 a and 115 b are likewise heavily doped with an N-type material toform the cathodes of the polycrystalline silicon diodes D₁, D₂, D₃, . .. , D_(n-1), D_(n). Each of the regions 120 a and 120 b, and the regions125 a and 125 b have metallic alloy salicides formed on their surfacesto create contacts that form connections to the metal layers 135, 140,145, and 150. The metal connection 135 is connected to the distributionnetwork 155 of the power supply voltage source V_(sup1). The metalconnections 140 and 145 provide the connections of the cathodes to theanodes to serially connect the polycrystalline silicon diodes D₁, D₂,D₃, . . . , D_(n-1), D_(n). The cathode of the last diode is coupled bythe metal connection 150 to the distribution network 160 of the powersupply voltage source V_(sup2).

[0052] A resistor protective oxide (RPO) is formed on the surface ofeach segment of the polycrystalline silicon 115 a and 115 b to protecteach segment of the polycrystalline silicon 115 a and 115 b, whileallowing the metal to alloy with the polycrystalline silicon 115 a and115 b during creation of the contacts and the metal layers 135, 140,145, and 150.

[0053] Refer now to FIGS. 5a-5 o and FIGS. 6a-6 b for a discussion ofthe method for the fabrication of the ESD protection circuit of thisinvention. The method begins with the depositing of a silicon nitride(Si_(x)N_(y)) layer 210 and a thick oxide layer 215 on a lightly dopedP-type substrate 205 to form a masking. Openings 220 are formed in thesilicon nitride (Si_(x)N_(y)) layer 210 and a field oxide layer 215 inlocations that are to form the regions of shallow trench isolation 10 aand 110 b of FIG. 4b. The P-type silicon substrate 205 is then etched inthe openings 220 to form the shallow trenches 225 in the surface of theP-type substrate 205. Each of the trenches 225 are then lined with awith an insulation layer 230 and then further filled with an insulationmaterial 235 such as silicon dioxide to form the shallow trenchisolation.

[0054] The silicon nitride (Si_(x)N_(y)) layer 210 and the thick oxidelayer 215 are removed generally by a chemical-mechanical planarization(CMP) that is well known in the art. A layer of polycrystalline silicon240 is deposited on the surface of the P-type substrate 205 with amasking layer 245 being al formed on the layer of polycrystallinesilicon 240. Blocking areas 250 are formed in the masking layer 245 todefine the locations of the segments of the polycrystalline silicon 115a and 115 b of FIG. 4b.

[0055] The layer of polycrystalline silicon 240 is then etched to formthe segments of the polycrystalline silicon 255 a, 255 b, 255 c, and 255d. A masking layer 260 is then formed on the surface of the P-typesubstrate 205 and the segments of polycrystalline silicon 255 a, 255 b,255 c, and 255 d. Openings 265 are formed in the masking layer 260. AP-type acceptor impurity 275 such as boron, gallium, or indium isdiffused through the openings 265 into the segments of polycrystallinesilicon 255 a, 255 b, 255 c, and 255 d to form the P-type anodes 257 a,257 b, 257 c, and 257 d of the polycrystalline silicon diodes. Themasking layer 260 is then removed and the masking layer 280 is thenformed on the surface of the P-type substrate 205 and the segments ofpolycrystalline silicon 255 a, 255 b, 255 c, and 255 d. Openings 285 areformed in the masking layer 260. A N-type donor impurity 290 such asantimony, phosphorus, or arsenic is diffused through the openings 285into the segments of polycrystalline silicon 255 a, 255 b, 255 c, and255 d to form the N-type cathodes 259 a, 259 b, 259 c, and 259 d of thepolycrystalline silicon diodes.

[0056] The masking layer 280 is removed and the insulative material 295such as silicon dioxide is deposited upon the surface of the P-typesubstrate 205 and the segments of polycrystalline silicon 255 a, 255 b,255 c, and 255 d that now form the polycrystalline silicon diodes.Blocking areas 305 are formed in the masking layer 300 to protect thedesired regions of the insulative material 295. The masking layer 300 isremoved and the insulative layer 300 is etched to form the resistorprotective oxide (RPO) 295 a, 295 b, 295 c, and 295 d and the fieldinsulation areas 290.

[0057] A metal such as titanium is deposited and alloyed to the segmentsof polycrystalline silicon 255 a, 255 b, 255 c, and 255 d in the exposedareas to form the contacts 312 a, 312 b, 312 c, and 312 d on the P-typeregions 257 a, 257 b, 257 c, and 257 d and the contacts 314 a, 314 b,314 c, and 314 d on the N-type regions 259 a, 259 b, 259 c, and 259 d.During the deposition of the metal 310, the resistor protective oxide295 a, 295 b, 295 c, and 295 d protects the junction of the adjoinedP-type regions 257 a, 257 b, 257 c, and 257 d and N-type regions 259 a,259 b, 259 c, and 259 d.

[0058] The masking layer 325 is deposited on the metal 310 and theopening 320 are formed to demarcate the connections of the ESDprotection circuit of this invention. The exposed metal 325 is etched toremove the excess so as to form the metal traces 335, 340, 345, 350, 365to complete the interconnection of the ESD protection circuit. The anodeof the diode D₁ is connected through the metal trace to the distributionnetwork 355 to the power supply voltage source V_(sup1). The cathode ofthe diode D₁ is connected to the anode of the diode D₂ by the metaltrace 340. The cathode of the diode D₂ is connected to the anode of thediode D₃ by the metal trace 345. The cathode of the diode D₃ isconnected to the anode of the diode D₄ by the metal trace 350. Thecathode of the diode D₄ is connected to the distribution network 360 ofthe power supply voltage source V_(sup2) by the metal trace 365. Thisstructure as described forms the serially connected string of diodes D₁,D₂, D₃, D₄ between the power supply voltage source V_(sup1) and thepower supply voltage source V_(sup2).

[0059] The width W (FIG. 6a) of the diodes and the thickness h (FIG. 5j)of the segments of polycrystalline silicon 255 a, 255 b, 255 c, and 255d and the doping levels of the P-type regions 257 a, 257 b, 257 c, and257 d and N-type regions 259 a, 259 b, 259 c, and 259 d determine theresistivity of the diode and thus the current capacity of the diodes D₁,D₂, D₃, D₄. The preferred doping concentration levels for the P-typeregions 257 a, 257 b, 257 c, and 257 d are from approximately 10¹⁵atoms/cm³ to approximately 1021 atoms/cm⁻³. The preferred dopingconcentration levels for the N-type regions 259 a, 259 b, 259 c, and 259d are from approximately 10¹⁵ atoms/cm⁻³ to approximately 10²¹atoms/cm⁻³. The preferred thickness h of the segments of polycrystallinesilicon 255 a, 255 b, 255 c, and 255 d is from approximately 1000 Å toapproximately 3000 Å. The width W of the segments of polycrystallinesilicon 255 a, 255 b, 255 c, and 255 d are preferably from approximately0.5 μm to approximately 100 μm.

[0060] Refer now to FIGS. 3 and 7 to compare the current through the ESDprotection circuit of the prior art as illustrated in FIG. 1 and the ESDprotection circuit of this invention as illustrated in FIG. 4b. Thecomparison of the voltage level across the ESD protection circuits ofthe prior art and of this invention having one, five and seven stages isshown in Table 1 TABLE 1 Prior Art (FIG. 1) This invention (FIG. 4b)Number of Stages/Circuit Voltage @ 1 μa Voltage @ 1 μa 1 Stage 0.65 V0.60 5 Stages  2.7 V 2.9 V 7 Stages  3.2 V 4.0 V

[0061] Further, when the slopes of the plots for the single stage 80,five stages 85, and seven stages 90 of the prior art are compared withthe slopes of the single stage 380, five stages 385, and seven stages390 of this invention, it becomes apparent that the threshold voltage ofthe ESD protection circuit of the prior art is not linear as the numberof stages is increased. However, the threshold voltage of the ESDprotection circuit of this invention is more nearly linear with theincrease in the number of stages or diodes in the string.

[0062] The number of the serially connected polycrystalline silicondiodes D₁, D₂, D₃, . . . , D_(n-1), D_(n) of FIG. 4b included in theelectrostatic discharge circuit of this invention is determined by theamount of noise or change beyond the difference between the voltagelevels of the power supply voltage source V_(sup1) and the power supplyvoltage source V_(sup2) that can be tolerated by the internal integratedcircuits and can be calculated by the formula:$n \geq \frac{V_{noise} + {{{Vx1} - {Vx2}}}}{V_{T}}$

[0063] where:

[0064] n is the number serially connected of polycrystalline silicondiodes,

[0065] V_(noise) is the maximum voltage level difference allowed to bepresent on the internal integrated circuits between the first powersupply voltage source and the second power supply voltage source,

[0066] Vx1 is the magnitude of the first power supply voltage sourceV_(sup1),

[0067] Vx2 is the magnitude of the second power supply voltage sourceV_(sup2), and

[0068] V_(T) is the threshold voltage of each polycrystalline silicondiodes.

[0069] While this invention has been particularly shown and describedwith reference to the preferred embodiments thereof, it will beunderstood by those skilled in the art that various changes in form anddetails may be made without departing from the spirit and scope of theinvention. In particular the doping types and concentrations are shownas having particular polarities. It is in keeping with the intent ofthis invention that the doping types and concentrations may be varied byprocedures and methods known in the art. In particular, the shallowtrench isolation 110 a 110 b of FIG. 4 maybe a field oxide region.

The invention claimed is:
 1. An electrostatic discharge circuitconnected between a first power supply voltage source and a second powersupply voltage source to protect internal integrated circuits fromdamage due to an electrostatic discharge, said electrostatic dischargecircuit comprising: a plurality of serially connected polycrystallinesilicon diodes formed on a surface of a substrate, each diode having afirst electrode and second electrode, said plurality of seriallyconnected polycrystalline diodes including a first diode of theplurality of 9 diodes has its first electrode connected to the firstpower supply voltage source, and a last diode having its secondelectrode connected to the second power supply voltage source, whereinthe first electrode is a first region of a polycrystalline silicon beingheavily doped with an impurity of a first type and the second electrodeis a second region of a polycrystalline silicon being heavily doped withan impurity of a second type, said second region being adjoined to thefirst region to form an electrical junction.
 2. The electrostaticdischarge circuit of claim 1 wherein the adjoined first and secondregions of each diode are formed on shallow trench isolation formedwithin the substrate.
 3. The electrostatic discharge circuit of claim 1wherein each diode further comprises a resistor protection oxide formedto overlay a portion of the first and second regions at the junction. 4.The electrostatic discharge circuit of claim 1 wherein the firstelectrode of each polycrystalline silicon diode is a cathode and thesecond electrode of each polycrystalline silicon diode is an anode. 5.The electrostatic discharge circuit of claim 4 wherein the impurity ofthe first type is an N-type impurity having a density of fromapproximately 10¹⁵ atoms/cm⁻³ to approximately 10²¹ atoms/cm⁻³.
 6. Theelectrostatic discharge circuit of claim 4 wherein the impurity of thesecond type is a P-type impurity having a density of from approximately10¹⁵ atoms/cm⁻³ to approximately 10²¹ atoms/cm⁻³.
 7. The electrostaticdischarge circuit of claim 4 wherein each of the polycrystalline diodeshas a thickness of from approximately 1000 Å to approximately 3000 Å. 8.The electrostatic discharge circuit of claim 4 wherein each of thepolycrystalline diodes has a thickness of from approximately 0.5 μm toapproximately 100 μm.
 9. The electrostatic discharge circuit of claim 1wherein a number of the plurality of serially connected polycrystallinesilicon diodes is determined by the formula:$n \geq \frac{V_{noise} + {{{Vx1} - {Vx2}}}}{V_{T}}$

where: n is the number serially connected of polycrystalline silicondiodes, V_(noise) is the maximum voltage level difference allowed to bepresent on the internal integrated circuits between the first powersupply voltage source and the second power supply voltage source, Vx1 isthe magnitude of the first power supply voltage source, Vx2 is themagnitude of the second power supply voltage source, and V_(T) is thethreshold voltage of each polycrystalline silicon diodes.
 10. Anintegrated circuit formed on a substrate comprising: a first powerdistribution network connected to a first power supply voltage source; asecond power distribution network connected to a second power supplyvoltage source; a plurality of internal circuits connected between thefirst and second power distribution networks; and an electrostaticdischarge circuit connected between a first power supply voltage sourceand a second power supply voltage source to protect said internalcircuits from an ESD event, said electrostatic discharge circuitcomprising: a plurality of serially connected polycrystalline silicondiodes formed on a surface of a substrate, each diode having a firstelectrode and second electrode, said plurality of serially connectedpolycrystalline diodes including a first diode of the plurality ofdiodes has its first electrode connected to the first power supplyvoltage source, and a last diode having its second electrode connectedto the second power supply voltage source, wherein the first electrodeis a first region of a polycrystalline silicon being heavily doped withan impurity of a first type and the second electrode is a second regionof a polycrystalline silicon being heavily doped with an impurity of asecond type, said second region being adjoined to the first region toform an electrical junction.
 11. The integrated circuit of claim 10wherein the adjoined first and second regions of each diode are formedon shallow trench isolation formed within the substrate.
 12. Theintegrated circuit of claim 10 wherein each diode further comprises aresistor protection oxide formed to overlay a portion of the first andsecond regions at the junction.
 13. The integrated circuit of claim 10wherein the first electrode of each polycrystalline silicon diode is acathode and the second electrode of each polycrystalline silicon diodeis an anode.
 14. The integrated circuit of claim 13 wherein the impurityof the first type is an N-type impurity having a density of fromapproximately 10¹⁵ atoms/cm⁻³ to approximately 10²¹ atoms/cm⁻³.
 15. Theintegrated circuit of claim 13 wherein the impurity of the second typeis a P-type impurity having a density of from approximately 10¹⁵atoms/cm⁻³ to approximately 10²¹ atoms/cm³.
 16. The integrated circuitof claim 13 wherein each of the polycrystalline diodes has a thicknessof from approximately 1000 Å to approximately 3000 Å.
 17. The integratedcircuit of claim 13 wherein each of the polycrystalline diodes has athickness of from approximately 0.5 μm to approximately 100 μm.
 18. Theintegrated circuit of claim 10 wherein a number of the plurality ofserially connected polycrystalline silicon diodes is determined by theformula: $n \geq \frac{V_{noise} + {{{Vx1} - {Vx2}}}}{V_{T}}$

where: n is the number of serially connected polycrystalline silicondiodes, V_(noise) is the maximum voltage level difference allowed to bepresent on the internal integrated circuits between the first powersupply voltage source and the second power supply voltage source, Vx1 isthe magnitude of the first power supply voltage source, Vx2 is themagnitude of the second power supply voltage source, and V_(T) is thethreshold voltage of each polycrystalline silicon diodes.
 19. A methodfor forming an electrostatic discharge circuit comprising seriallyconnected polycrystalline silicon diodes, said method comprising thesteps of: providing a substrate; forming polycrystalline silicon membersupon said substrate: doping a first portion of each of saidpolycrystalline silicon members with an impurity of a first type; dopinga second portion of each of said polycrystalline silicon members with animpurity of a second type such that a junction is formed where the firstportion of each of said polycrystalline silicon members adjoins saidsecond portion of said polycrystalline members; connecting the secondportion of one polycrystalline section to the first portion of asubsequent polycrystalline silicon member; connecting the first portionof a first polycrystalline silicon member to a first power supplyvoltage source; and connecting the second portion of a lastpolycrystalline silicon member to a second power supply voltage source.20. The method of claim 19 further comprising the step of: forming aplurality of shallow trench isolation regions, each polycrystallinesilicon member being formed on one of said isolation regions.
 21. Themethod of claim 1 further comprising the step of: forming a resistorprotection oxide member upon each of the polycrystalline silicon membersto overlay said junction.
 22. The method of claim 19 wherein theconnecting the first and second portions of the polycrystalline siliconmembers comprises the steps of: alloying a metal into top surfaces ofthe first and second portions of each of the polycrystalline siliconmembers to form contact areas; and forming connecting metallization incontact with the contact areas of the first and second portions of eachpolycrystalline silicon member and between the second portion of eachpolycrystalline silicon member and the first portion of the subsequentpolycrystalline silicon member, the first portion of the firstpolycrystalline silicon member, and the second portion of the lastpolycrystalline silicon member.
 23. The method of claim 19 wherein thefirst portion of each of the polycrystalline silicon members is acathode of each polycrystalline silicon diode and the second portion ofeach of the polycrystalline members is an anode of each polycrystallinesilicon diode.
 24. The method of claim 19 wherein the impurity of thefirst type is an N-type impurity having a density of from approximately10¹⁵ atoms/cm⁻³ to approximately 10²¹ atoms/cm⁻³.
 25. The method ofclaim 19 wherein the impurity of the second type is a P-type impurityhaving a density of from approximately 10¹⁵ atoms/cm⁻³ to approximately10²¹ atoms/cm⁻³.
 26. The method of claim 19 wherein each of thepolycrystalline silicon members has a thickness of from approximately1000 Å to approximately 3000 Å.
 27. The method of claim 19 wherein eachof the polycrystalline silicon members has a thickness of fromapproximately 0.5 μm to approximately 100 μm.
 28. The method of claim 19wherein a number of the serially connected polycrystalline silicondiodes is determined by the formula.$n \geq \frac{V_{noise} + {{{Vx1} - {Vx2}}}}{V_{T}}$

where: n is the number serially connected of polycrystalline silicondiodes, V_(noise) is the maximum voltage level difference allowed to bepresent on the internal integrated circuits between the first powersupply voltage source and the second power supply voltage source, Vx1 isthe magnitude of the first power supply voltage source, Vx2 is themagnitude of the second power supply voltage source, and V_(T) is thethreshold voltage of each polycrystalline silicon diodes.